asic-puzzle-2026
Tech stack & purpose
Jane Street created this ASIC reverse-engineering puzzle, which challenges participants to understand and extract the logic from a complex integrated circuit design by analyzing its physical layout representation. The puzzle provides a GDS file (the standard format for circuit layouts) that can be inspected using tools like KLayout or the TinyTapeout Online GDS Viewer, along with example input files in VCD format viewable with tools like Surfer. To help participants develop their reverse-engineering approaches, the repository includes a warm-up puzzle consisting of a simple Verilog design with shift registers, an adder, and a comparator, accompanied by intermediate files showing the progression from original source code through synthesis, placement and routing, to final manufacturable layout.
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- asinghani1 commits