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bsc

Bluespec Compiler (BSC)

GitHub
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1,127commits
61contributors
14languages

Tech stack & purpose

The Bluespec Compiler (BSC) is an open-source compiler for Bluespec SystemVerilog (BSV), a hardware design language. The repository contains numerous examples and libraries demonstrating BSV's capabilities across digital design domains including FIR filters, memory systems, cellular automata, bus protocols, and signal processing. BSV is built on a synchronous design model with features for managing clock domains, automatic pipeline control through rule-based execution, and seamless interoperability with Verilog through imports and RTL generation. The compiler generates Verilog output and supports simulation, and the repository includes supporting tools such as a VIM syntax highlighting mode for BSV development.

Community & reference links

Languages

Haskell
59.8%
Bluespec
16.0%
Emacs Lisp
12.5%
C++
4.8%
Verilog
3.3%
Shell
1.0%
Tcl
0.9%
C
0.8%
Makefile
0.6%
Vim Script
0.3%
Smalltalk
0.0%
Perl
0.0%
Python
0.0%
Dockerfile
0.0%

Contributors (top 30 of 61)