riscv-isa-sim

Tech stack & purpose

Spike is a RISC-V instruction set simulator that implements a functional model of one or more RISC-V processors. The project supports a comprehensive range of RISC-V ISA features including base integer instruction sets (RV32I, RV64I, RV32E, RV64E), numerous standard extensions (M, A, F, D, C, V, and others), cryptographic extensions, and privileged modes (Machine, Supervisor, and User). Spike can be used as a target for the RISC-V Architectural Test framework and supports interactive debugging via debug mode, gdb with OpenOCD, and configuration options such as selecting between 32-bit and 64-bit operation and testing individual instruction set extensions. The simulator is built using C++, integrates with standard tooling like device-tree-compiler and Boost libraries, and provides both functional instruction simulation and memory management capabilities.

Languages

Contributors (top 30 of 238)

• Andrew Waterman1,797 commits
• Scott Johnson351 commits
• Chih-Min Chao296 commits
• Tim Newsome282 commits
• YenHaoChen229 commits
• Jerry Zhao192 commits
• Yunsup Lee77 commits
• Weiwei Li77 commits
• Binno34 commits
• Rupert Swarbrick31 commits
• Ved Shanbhogue30 commits
• Palmer Dabbelt26 commits
• Anup Patel24 commits
• Scott Beamer19 commits
• Megan Wachs18 commits
• Ryan Buchner18 commits
• Parshintsev Anatoly17 commits
• Alexander Romanov16 commits
• mslijepc15 commits
• marcfedorow14 commits
• rbuchner13 commits
• Ming-Yi Lai12 commits
• Elmar Melcher12 commits
• Philipp Tomsich12 commits
• 
  Prashanth Mundkur11 commits · 54 followers
• Eric Gouriou11 commits
• Yueh-Ting (eop) Chen11 commits
• Atul Khare10 commits
• Mark Fedorov10 commits
• Wesley W. Terpstra10 commits