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clash-compiler

Haskell to VHDL/Verilog/SystemVerilog compiler

GitHubclash-lang.org/
asicfpgahardware-description-languagehaskellsystemverilogverilogvhdl
Browse cluster: Haskell tooling and libraries →
6,433commits
84contributors
9languages

Tech stack & purpose

Clash is a functional hardware description language that borrows syntax and semantics from Haskell, compiling high-level hardware descriptions to synthesizable VHDL, Verilog, or SystemVerilog. The project is built in Haskell and uses GHC as its compiler front-end, with support for multiple GHC versions across Linux, Windows, and macOS. Key features include strong typing with type inference, an interactive REPL for testing designs, higher-order functions, synchronous sequential circuit design using Signals, and type-safe multi-clock-domain support. The project is maintained by an active open-source community with discussion forums on Discourse, Discord, and social media platforms.

Community & reference links

Languages

Haskell
98.7%
Tcl
0.4%
Nix
0.4%
Shell
0.4%
Dockerfile
0.1%
Python
0.1%
PowerShell
0.0%
C
0.0%
CSS
0.0%

Contributors (top 30 of 84)